A typical solid state field effect transistor (FET) has gate, source, and drain contact structures, each of which are electrically connected to a corresponding channel region, source region, and drain region, respectively, within a semiconductor substrate. Bond pads are electrically connected to the drain and gate contact structures to provide for external connectivity to the FET.
The physical proximity of the gate and drain contact structures leads to electromagnetic coupling between the structures, and more particularly to parasitic feedback capacitance between the gate and drain structures, referred to as Cgd. Cgd is a critical parameter, and relatively high Cgd values contribute to device performance degradation, especially at higher frequencies. More particularly, device gain and stability may be detrimentally affected in device designs with relatively high Cgd.